EDN

Two gates and a microprocessor form digital PLL

You can use Microchip's low-cost PIC16F818 microprocessor and a pair of gates to construct a digital PLL that can clean noisy digital signals over a range of 4 to 40 kHz. Featuring programmable lock ...
Design-Reuse

PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

Input 20M-200MHz, output 250M-500MHz (with duty ratio 40%~60%) and 125M~ 250MHz (with duty ratio 45%~ 55%), frequency synthesizable PLL, UMC 0.13um HS/FSG Logic ...
Electronic Design

Digital PLL Perks Up Performance In T1-E1, Other TDM Apps

Thanks to a digital phase-locked loop (DPLL), the ZL30109 DS1/E1 System Synchronizer chip brings timing and synchronization to multitrunk DS1 and E1 transmission equipment. DPLLs typically use a DSP ...
EDN

Build a digital PLL with three ICs

The simple circuit in this DesignIdea exhibits the basic characteristicsof a traditional analog phase-lockedloop but has no analog componentsother than the reference oscillator.Other digital PLLs ...
Design-Reuse

Achieving Groundbreaking Performance with a Digital PLL

Digital PLLs outperform analog PLLs in jitter, phase noise, power, and die area. They also reduce migration risk and cost. They make integration and production test easy. Yet, they have not been ...