EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
EDN

Altera Demonstrates Industry’s First Model-Based Floating-Point DSP Capabilities for FPGAs

The floating-point DSP design flow includes Altera's floating-point DSP compiler, which is integrated into the DSP Builder Advanced Blockset, Quartus® II RTL tool chain, and ModelSim simulator, as ...
Design-Reuse

Implementing matrix inversions in fixed-point hardware

We implement fixed-point matrix inversion on a Virtex-4 FPGA using a synthesizable QR-decomposition MATLAB model and the AccelDSP Synthesis tool. The resulting function occupies 12% of a XC4VSX55 ...
Design-Reuse

Altera Demonstrates Industry's First Model-Based Floating-Point DSP Capabilities for FPGAs

Altera's New Highly-Efficient Floating-Point DSP Design Flow Validated by BDTI, Industry's Most Trusted Source of Independent DSP Technology Analysis San Jose, Calif., September 12, 2011—Altera ...